Bojie Li (李博杰). I work on AI agents and personalization, LLM systems, and datacenter networking. Below are recent papers — most with an interactive companion site — followed by earlier systems research.
Couple a frozen reactive VLM and a frozen reasoning VLM, training only the channel between them — a learned latent bridge projects the slow model's residuals into the fast model's embedding space, no text round-trip, matching or beating a text bridge across Atari and driving.
A user's facts become a few rows in a content-addressed memory table rather than a rewrite of the model — per-user memory as a local, leak-free parametric edit.
Each successful run compiles into a small program the agent can replay — and every program is verified before it is trusted, so repeated tasks get faster without getting riskier.
Transformers memoize field-conditioned conclusions onto downstream tokens at prefill — making the KV cache something you can edit, compose, and reuse.
An agent's model of a user as a version-controlled software project of typed Python dataclasses and executable constraints — recall, aggregation, and proactive alerting in one medium.
A compact, statically verifiable instruction set that runs on the memory-side NIC, collapsing multi-RTT remote-memory indirection chains into a single round-trip.
The first clean-room open implementation of Huawei's Unified Bus transport. A native load/store path returns a 64-byte remote fetch in ~500 ns — 4.37× below a matched RoCEv2 baseline.
Estimating a black-box model's parameter count from its factual capacity — with calibration curves and probe-level data across 165 models and 1,400 questions.
Transport that carries meaning, not signal: discrete audio tokens and a hybrid screen representation cut uplink bandwidth 64× for audio and 130–210× for screenshots, within 0.7 pp of raw task accuracy.
Bridging the gap between interrupt and polling in RDMA on commodity hardware.
A polyhedral tensor compiler for NPUs with complex tiling and hierarchical fusion.
Causal and total-order message scatter via in-network computation.
High-performance user-space sockets, compatible and isolated, scaling to many cores.
Programmable-NIC key-value store: 180M ops/s per NIC at sub-10µs tail latency.
FPGA network processing in a C-like, modular language at 200M pps, <2µs latency.
Fault-tolerant SDN router: hitless component failure and upgrade.
Multi-path hardware transport for RDMA tuned for tiny on-NIC memory.
Making the RNIC stateless by shifting connection state across the trusted network, so the bottleneck side keeps zero per-connection state.
Memory-efficient loss recovery: up to 14× throughput with 23B per-flow state.
Loss recovery that exploits multi-path diversity by recovering on a less-lossy sub-flow.
An operating system for FPGAs to enable large-scale datacenter deployment.
Transparent, efficient fault tolerance for distributed apps on commodity Linux.
Real-time HTAP + streaming database with efficient serializability.
Synthesizing P4 data planes by learning the behavior of software apps.
A transparent FPGA PCIe bump-in-the-wire debugger and gateway.
Hiding offload latency by running non-conflicting work in event-driven apps.
Course-review site for USTC: 6,000+ users, 16,000+ reviews. Open source (AGPL).
FPGA RSA acceleration for HTTPS handshakes — throughput of ~20 CPU cores.
A smart global VPN with nearby ingress and destination-aware egress selection.